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1 for more information www.linear.com/ltm4650a typical application features description dual 25a or single 50a dc/dc module regulator with 1% dc accuracy the lt m ? 4650a is a dual 25a or single 50a output switching mode step-down dc/dc module ? (micromodule) regula - tor with 1% total dc output error. included in the package are the switching controllers, power fet s, inductors and all supporting components. operating from an input volt - age range of 4.5v to 16v, the ltm4650a supports two outputs with an output voltage range of 0.6v to 5.5v , each set by a single external resistor. its high efficiency design delivers up to 25a continuous current for each output. fast internal control loop compensation allows for fast transient response to minimize output capacitance when powering fpgas, asics, and processors. fault protection features include overvoltage and over - current protection. the ltm4650a is offered in 16mm 16mm 4.41mm lga an d16mm 16mm 5.01mm bga packages. 50a, 3.3v output dc/dc module regulator applications n dual 25a or single 50a output n input voltage range: 4.5v to 16v n output voltage range: 0.6v to 5.5v n 1% maximum total dc output error over line, load and temperature n higher light load efficiency and wider v out range than ltm4650-1 n differential remote sense amplifier n current mode control/fast transient response n multiphase parallel current sharing up to 300a n internal temperature monitor n pin compatible with the ltm4620a (dual 13a, single 26a) and ltm4630a (dual 18a, single 36a) n adjustable switching frequency or synchronization n overcurrent foldback protection n selectable burst mode ? operation, pulse-skipping mode operation n soft-start/voltage tracking n output overvoltage protection n 16mm 16mm 4.41mm lga and 16mm 16mm 5.01mm bga packages n telecom and networking equipment n storage and atca cards n industrial equipment all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. other patents pending. 3.3v out efficiency vs i out ltm4650 product family selection table v in range v out range i out compen- sation dc v out accuracy ltm4650 4.5v to 15v 0.6v to 1.8v 25a 2 internal 1.5% ltm4650-1b external ltm6450-1a 0.8% ltm4650a 4.5v to 16v 0.6v to 5.5v internal 1% ltm4650a-1 external 4650 0a 4650 f 40 6 00 6 50 0 40 6 00 6 0 0 5 4 45 6 4 load current (a) 0 65 efficiency (%) 90 85 80 75 70 100 95 20 30 40 50 10 4650a ta01b 5v in , 3.3v out , 600khz 12v in , 3.3v out , 600khz lt m4650a 4650afb
2 for more information www.linear.com/ltm4650a part number pad or ball finish part marking* package type msl rating total dc accuracy temperature? range (note 2) device finish code ltm4650aev#pbf au (rohs) ltm4650av e4 lga 3 1% C40c to 125c ltm4650aiv#pbf au (rohs) ltm4650av e4 lga 3 1% C40c to 125c ltm4650aey#pbf sac305 (rohs) ltm4650 ay e1 bga 3 1% C40c to 125c ltm4650aiy#pbf sac305 (rohs) ltm4650 ay e1 bga 3 1% C40c to 125c ltm4650aiy snpb (63/37) ltm4650ay e0 bga 3 1% C40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings: www.linear.com/packaging order information http://www.linear.com/product/ltm4650a#orderinfo pin configuration absolute maximum ratings v in (note 8) ................................................. C 0. 3v to 18v v sw1 , v sw2 .................................................... C 1v to 18v pgoo d1 , pgoo d2 , ru n1 , ru n2 , intv cc , extv cc .......................................... C 0. 3v to 6v mode_pllin , f set , trac k1 , trac k2 , diffout, phasmd ............................... C 0.3v to intv cc v out1 , v out2 , v out s1 , v out s2 (note 6) ........ C 0.3v to 6v (note 1) 44 6 6 44 4 5 6 0 f t jmax = 125c, ja = 7c/w, jcbottom = 1.5c/w, jctop = 3.7c/w, jb + jba ? 7c/w values defined per jesd51-12 weight = 3.6g bga package 144-lead (16mm 16mm 5.01mm) top view temp clkout sw1 phasmd extv cc 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a sw2 pgood1 pgood2 run2 track2 intv cc v outs2 diffp diffout diffn run1 track1 mode_pllin v fb1 v outs1 f set sgnd comp1 comp2 sgnd v fb2 v out2 gnd gnd sgnd gnd t jmax = 125c, ja = 7c/w, jcbottom = 1.5c/w, jctop = 3.7c/w, jb + jba ? 7c/w values defined per jesd51-12 weight = 3.8g diffp, diffn ......................................... C 0. 3v to intv cc com p1 , com p2 , v fb1 , v fb2 (note 6) ........ C 0.3v to 2.7v intv cc peak output current .................................. 5 0ma internal operating temperature range (note 2) ............................................. C 40 c to 125 c storage temperature range .................. C 55 c to 125 c peak package body temperature .......................... 245 c lt m4650a 4650afb
3 for more information www.linear.com/ltm4650a electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 34. symbol parameter conditions min typ max units v in input dc voltage l 4.5 16 v v out output voltage l 0.6 5.5 v v out1(dc) , v out2(dc) output voltage, total dc variation with line and load (note 8) c in = 22f 3, c out = 100f 1 ceramic, 470f poscap v in = 4.5v to 16v, v out = 1.2v, i out = 0a to 25a l 1.188 1.2 1.212 v input specifications v run1 , v run2 run pin on/off threshold run rising 1.1 1.25 1.40 v v run1hys , v run2hys run pin on hysteresis 150 mv i inrush(vin) input inrush current at start-up i out = 0a, c in = 22f 3, c ss = 0.01f, c out = 100f 3, v out1 = 1.2v, v out2 = 1.2v, v in = 12v 1 a i q(vin) input supply bias current (both channels on) v in = 12v, v out = 1.2v, burst mode operation v in = 12v, v out = 1.2v, pulse-skipping mode v in = 12v, v out = 1.2v, switching continuous shutdown, run = 0, v in = 12v 4.5 19 115 35 ma ma ma a i s(vin) input supply current v in = 5v, v out = 1.2v, i out = 25a v in = 12v, v out = 1.2v, i out = 25a 8.2 3.1 a a output specifications i out1(dc) , i out2(dc) output continuous current range v in = 12v, v out = 1.2v (note 7) 0 25 a v out1(line) /v out1 v out2(line) /v out2 line regulation accuracy for each output, v out = 1.2v, i out = 0a, v in from 4.5v to 16v l 0.02 0.1 %/v v out1 /v out1 v out2 /v out2 load regulation accuracy for each output, v in = 12v, v out = 1.2v, i out from 0a to 25a (note 7) l 0.1 0.4 % v out1(ac) , v out2(ac) output ripple voltage for each output, v in = 12v, v out = 1.2v, frequency = 450khz, i out = 0a, c out = 100f 3 ceramic, 470f poscap 15 mv p-p f s (each channel) output ripple voltage frequency v in = 12v, v out = 1.2v, f set = 1.25v (note 4) 500 khz f sync (each channel) sync capture range 250 780 khz v outstart (each channel) turn-on overshoot c out = 100f 3 ceramic, 470f poscap, v in = 12v , v out = 1.2v, i out = 0a 10 mv t start (each channel) t urn-on time c out = 100f 3 ceramic, 470f poscap, v in = 12v, no load, track/ss with 0.01f to gnd 5 ms v out(ls) (each channel) peak deviation for dynamic load load : 0% to 50% to 0% of full load c out = 100f 3 ceramic, 470f poscap, v in = 12v, v out = 1.2v 30 mv t settle (each channel) settling t ime for dynamic load step load: 0% to 50% to 0% of full load, v in = 12v, c out = 100f 3 ceramic, 470f poscap 20 s i out(pk) (each channel) output current limit v in = 12v, v out = 1.2v 30 a control section v fb1 , v fb2 voltage at v fb pins i out = 0a, v out = 1.2v l 0.595 0.600 0.605 v i fb (note 6) C5 C20 na v ovl feedback overvoltage lockout l 0.64 0.66 0.68 v lt m4650a 4650afb
4 for more information www.linear.com/ltm4650a electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 34. symbol parameter conditions min typ max units i track1 , i track2 track pin soft-start pull-up current track1,track2 start at 0v 1 1.25 1.5 a uvlo undervoltage lockout (falling) 3.3 v uvlo hysteresis 0.6 v t on(min) minimum on-time (note 6) 90 ns r fbhi1 , r fbhi2 resistor between v outs1 , v outs2 and v fb1 , v fb2 pins for each output 60.05 60.4 60.75 k? v pgood1 , v pgood2 low pgood v oltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 5 a v pgood pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % % int v cc linear regulator v intvcc internal v cc voltage 6v < v in < 16v 4.8 5 5.2 v v intvcc load regulation int v cc load regulation i cc = 0ma to 50ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v extvcc(drop) extv cc dropout i cc = 20ma, v extvcc = 5v 50 100 mv v extvcc(hyst) extv cc hysteresis 220 mv oscillator and phase-locked loop frequency nominal nominal frequency f set = 1.2v 450 500 550 khz frequency low lowest frequency f set = 0v (note 5) 210 250 290 khz frequency high highest frequency f set > 2.4v, up to intv cc 700 780 860 khz f set frequency set current 9 10 11 a r mode_pllin mode_pllin input resistance 250 k clkout phase (relative to v out1 ) phasmd = gnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg clk high clk low clock high output v oltage clock low output voltage 2 0.2 v v differential amplifier a v differential amplifier gain 1 v/v r in input resistance measured at diffp input 80 k? v os input offset voltage v diffp = v diffout = 1.2v, i diffout = 100a 3 mv psrr differential amplifier power supply rejection ratio 4.5v < v in < 16v 90 db i cl maximum output current 3 ma v out(max) maximum output voltage i diffout = 300a intv cc C 1.4 v gbw gain bandwidth product 3 mhz v temp diode connected pnp i = 100a 0.6 v tc temperature coefficient l C2.2 mv/c lt m4650a 4650afb
5 for more information www.linear.com/ltm4650a electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4650a is tested under pulsed load conditions such that t j t a . the ltm4650ae is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4650ai is guaranteed over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: two outputs are tested separately and the same testing condition is applied to each output. note 4: the switching frequency is programmable from 250khz to 780khz. note 5: ltm4650a device is designed to operate from 250khz to 780khz note 6: these parameters are tested at wafer sort. note 7: see output current derating curve for different ambient temperature. note 8: total dc output voltage error includes all errors over temperature?C reference, line and load regulation as well as the tolerance of the integrated top feedback resistor. lt m4650a 4650afb
6 for more information www.linear.com/ltm4650a typical performance characteristics burst mode and pulse-skip mode efficiency v in =12v, v out = 1.2v, f s = 300khz 1v dual phase single output load transient response (ceramic cap) efficiency vs output current, v in = 5v efficiency vs output current, v in = 12v 1.2v dual phase single output load transient response (ceramic cap) 1.5v dual phase single output load transient response (ceramic cap) 1.8v dual phase single output load transient response (ceramic cap) 2.5v dual phase single output load transient response (ceramic cap) 3.3v dual phase single output load transient response (ceramic cap) load current (a) 0 65 efficiency (%) 90 85 80 75 70 100 95 10 15 20 25 5 4650a g01 2.5v out , 500khz 3.3v out , 600khz 1.8v out , 500khz 1.5v out , 400khz 1.2v out , 400khz 1.0v out , 300khz load current (a) 0 65 efficiency (%) 90 85 80 75 70 100 95 10 15 20 25 5 4650a g02 2.5v out , 500khz 3.3v out , 600khz 1.8v out , 500khz 5.0v out , 750khz 1.5v out , 400khz 1.2v out , 400khz 1.0v out , 300khz ccm pulse-skip mode burst mode operation lt m4650a 4650afb 30 40 50 60 70 80 90 100 efficiency (%) 4650a g03 load current (ma) v out (ac) 50mv/div load step 10a/div 50s/div 4650a g04 12v in , 1v out, 300khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf v out (ac) 50mv/div 0.01 load step 10a/div 50s/div 4650a g05 12v in , 1.2v out, 400khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf v out (ac) 50mv/div load step 10a/div 50s/div 4650a g06 0.1 12v in , 1.5v out, 400khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf v out (ac) 50mv/div load step 10a/div 50s/div 4650a g07 12v in , 1.8v out, 500khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf v out (ac) 50mv/div 1 load step 10a/div 50s/div 4650a g08 12v in , 2.5v out, 500khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf v out (ac) 100mv/div load step 10a/div 50s/div 10 4650a g09 12v in , 3.3v out, 600khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf 0 10 20
7 for more information www.linear.com/ltm4650a typical performance characteristics 1.8v dual phase single output load transient response (poscap) 2.5v dual phase single output load transient response (poscap) 1.2v dual phase single output load transient response (poscap) 1.5v dual phase single output load transient response (poscap) 1v dual phase single output load transient response (poscap) 5v dual phase single output load transient response (ceramic cap) 5v dual phase single output load transient response (poscap) 3.3v dual phase single output load transient response (poscap) lt m4650a 4650afb v out (ac) 50mv/div load step 10a/div 50s/div 4650a g12 12v in , 1.2v out, 400khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff v out (ac) 50mv/div load step 10a/div 50s/div 4650a g13 12v in , 1.5v out, 400khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff v out (ac) 50mv/div load step 10a/div 50s/div 4650a g14 12v in , 1.8v out, 500khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff v out (ac) 100mv/div v out (ac) 50mv/div load step 10a/div 50s/div 4650a g15 12v in , 2.5v out, 500khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff v out (ac) 100mv/div load step 10a/div 50s/div 4650a g16 12v in , 3.3v out, 600khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff v out (ac) 100mv/div load step 10a/div 50s/div 4650a g17 12v in , 5v out, 750khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff load step 10a/div v out (ac) 50mv/div load step 10a/div 50s/div 4650a g11 12v in , 1v out, 300khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 4 470f poscap + 8 100f ceramic no c ff 50s/div 4650a g10 12v in , 5v out, 750khz, dual phase single output 25%, 12.5a load step-up and step-down, 10a/ s slew rate c out = 16 100f ceramic cap c ff = 47pf
8 for more information www.linear.com/ltm4650a single phase short-circuit protection with 25a load single phase start-up with 25a load single phase short-circuit protection with no load single phase start-up with no load typical performance characteristics lt m4650a 4650afb v out 0.5v/div input current 2a/div 20ms/div 4650a g19 12v in , 1.2v out, 400khz c out = 2 470f spcap + 4 100 f ceramic cap c ss = 0.1f sw 10v/div v out 0.5v/div input current 5a/div 100s/div sw 10v/div 4650a g20 12v in , 1.2v out, 400khz c out = 2 470f spcap + 4 100f ceramic cap sw 10v/div v out 0.5v/div input current 2a/div 100s/div 4650a g21 12v in , 1.2v out, 400khz c out = 2 470f spcap + 4 100f ceramic cap v out 0.5v/div input current 0.2a/div 20ms/div 4650a g18 12v in , 1.2v out, 400khz c out = 2 470f spcap + 4 100 f ceramic cap c ss = 0.1f sw 10v/div
9 for more information www.linear.com/ltm4650a pin functions v out1 ( a1Ca5, b1Cb5, c1Cc4): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. review table 6. gnd ( a6Ca7, b6Cb7, d1Cd4, d9Cd12, e1Ce4, e10Ce12, f1Cf3, f10Cf12, g1, g3, g10, g12, h1Ch7, h9Ch12, j1, j5, j8, j12, k1, k5Ck8, k12, l1, l12, m1 , m12): power ground pins for both input and output returns. v out2 ( a8Ca12, b8Cb12, c9Cc12): power output pins. apply output load between these pins and gnd pins. rec- ommend placing output decoupling capacitance directly between these pins and gnd pins. review t able 6. v outs1 , v outs2 ( c5, c8): this pin is connected to the top of the internal top feedback resistor for each output. the pin can be directly connected to its specific output, or connected to diffout when the remote sense amplifier is used. in paralleling modules, one of the v outs pins is connected to the diffout pin in remote sensing or directly to v out with no remote sensing. it is very important to connect these pins to either the diffout or v out since this is the feedback path, and cannot be left open. see the applications information section. f set (c6): frequency set pin. a 10a current is sourced from this pin. a resistor from this pin to ground sets a voltage that in turn programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications information section. sgnd ( c7, d6, g6C g7, f6 C f7 ): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the ap - plication. see layout guidelines in figure 14. v fb1 , v fb2 ( d5, d7): the negative input of the error am - plifier for each channel. internally, this pin is connected to v outs1 or v outs2 with a 60.4k? precision resistor. different output voltages can be programmed with an ad - ditional resistor between v fb and gnd pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. do not drive this pin. track1, track2 ( e5, d8): output voltage tracking pin and soft-start inputs. each channel has a 1.3a pull-up current source. when one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. the remaining channel can be set up as the slave, and have the masters output applied through a voltage divider to the slave out - puts track pin. this voltage divider is equal to the slave output s feedback divider for coincidental tracking. see the applications information section. comp1, comp2 ( e6, e7): current control threshold and error amplifier compensation point for each channel. the current comparator threshold increases with this control voltage. this device is internal compensated. see applica - tions information section. tie the comp pins together for parallel operation. do not drive this pin. diffp ( e8): positive input of the remote sense amplifier. this pin is connected to the remote sense point of the output voltage. diffamp can be used for 3.3v outputs. see the applications information section. diffn (e9): negative input of the remote sense amplifier. this pin is connected to the remote sense point of the output gnd. diffamp can be used for 3.3v outputs. see the applications information section. mode_pllin (f4): force continuous mode, burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels into force continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. run1, run2 ( f5, f9): run control pin. a voltage above 1.25v will turn on each channel in the module. a voltage below 1.25v on the run pin will turn off the related chan - nel. each run pin has a 1a pull-up current, once the run pin reaches 1.2v an additional 4.5a pull-up current is added to this pin. (recommended to use test points to monitor signal pin connections.) package row and column labeling may vary among module products. review each package layout carefully. lt m4650a 4650afb
10 for more information www.linear.com/ltm4650a pin functions diffout (f8): internal remote sense amplifier output. connect this pin to v outs1 or v outs2 depending on which output is using remote sense. in parallel operation con - nect one of the v outs pin to diffout for remote sensing. sw1, sw2 ( g2, g11): switching node of each channel that is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. see the applications information section. phasmd (g4): connect this pin to sgnd, intv cc , or float- ing this pin to select the phase of clkout to 60 degrees, 120 degrees, and 90 degrees respectively . clkout (g5): clock output with phase control using the phasmd pin to enable multiphase operation between devices. see the applications information section. pgood1, pgood2 ( g9, g8 ): output voltage power good indicator. open drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. intv cc (h8): internal 5v regulator output. the control circuits and internal gate drivers are powered from this voltage. decouple this pin to pgnd with a 4.7f low esr tantalum or ceramic. intv cc is activated when either run1 or run2 is activated. temp (j6): temperature monitor. an internal diode con - nected npn transistor connected between temp and sgnd pins. see the applications information section. ext v cc (j7): external power input that is enabled through a switch to intv cc whenever extv cc is greater than 4.7v. do not exceed 6v on this input, and connect this pin to v in when operating v in on 5v. an efficiency increase will occur that is a function of the (v in C intv cc ) multiplied by power mosfet driver current. typical current requirement is 30ma . v in must be applied before extv cc , and extv cc must be removed before v in . v in ( m2C m11 , l2 C l11, j2 C j4, j9 C j11, k2C k4 , k9C k11): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. heat sink (top exposed metal) : the top exposed metal is electrically unconnected. (recommended to use test points to monitor signal pin connections.) lt m4650a 4650afb
11 for more information www.linear.com/ltm4650a simplified block diagram decoupling requirements symbol parameter conditions min typ max units c in1, c in2 c in3, c in4 external input capacitor requirement (v in1 = 4.5v to 16v, v out1 = 1.2v) (v in2 = 4.5v to 16v, v out2 = 3.3v) i out1 = 25a i out2 = 25a 22 22 66 66 f f c out1 c out2 external output capacitor requirement (v in1 = 4.5v to 16v, v out1 = 1.2v) (v in2 = 4.5v to 16v, v out2 = 3.3v) i out1 = 25a i out2 = 25a 300 300 600 600 f f t a = 25c. use figure 1 configuration. figure 1. simplified ltm4650a block diagram 4650a bd temp clkout run1 mode_pllin phasemd track1 = 100a or temp monitors 4.7f ss cap 0.1f c in1 22f 25v v in v in c in2 22f 25v r fb2 13.3k mtop1 mbot1 power control 0.22f 0.22h 60.4k c out1 r fb1 40.2k + v out1 1.5v 25a v out2 3.3v 25a v fb1 gnd gnd v in 4.5v to 16v gnd gnd sw2 sw1 pgood2 pgood1 internal filter 0.1f c in3 22f 25v mtop2 mbot2 c in4 22f 25v 0.22f 0.22h c out2 + + ? 60.4k v out1 v out2 v fb2 v outs2 v outs1 r fset v in r t v in r t ss cap diffout diffn diffp comp1 track2 intv cc extv cc run2 comp2 f set sgnd internal comp internal comp sgnd lt m4650a 4650afb
12 for more information www.linear.com/ltm4650a operation power module description the ltm4650 a is a dual-output standalone nonisolated switching mode dc/dc power supply with 1% total dc output error over line, load and temperature variation. it can provide two 25a outputs or single 50a output with few external input and output capacitors and setup com - ponents. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5.5v dc over 4.5v to 16v input voltages. the typical application schematic is shown in figure 32. the ltm4650 a has dual integrated constant-frequency current mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is 300khz to 750khz depending on different input and output conditions. for switching-noise sensi - tive applications, it can be externally synchronized from 250khz to 780khz . a resistor can be used to program a free run frequency on the f set pin. see the applications information section. with current mode control, multi ltm4650 as can be easily paralleled to provide up to 300a current with guaranteed perfect current sharing. also, with current mode control, the ltm4650 a module is able to achieve sufficient stability margins and a fast transient response with a minimum number of output capacitors, even with all ceramic output capacitors. see applications information section. current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. internal overvoltage and undervoltage comparators pull the open-drain pgood outputs low if the output feedback voltage exits a 10% window around the regulation point. as the output voltage exceeds 10% above regulation, the bottom mosfet will turn on to clamp the output voltage. the top mosfet will be turned off. this overvoltage protect is feedback voltage referred. pulling the run pins below 1.1v forces the regulators into a shutdown state, by turning off both mosfets. the track pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. see the applications information section. the ltm4650 a is internally compensated to be stable over all operating conditions. table 6 provides a guideline for input and output capacitances for several operating con - ditions. the ltpowercad ? will be provided for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. a differential remote sense amplifier is available for sens - ing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. high efficiency at light loads can be accomplished with selectable burst mode operation or pulse-skipping opera - tion using the mode_pllin pin. these light load features will accommodate batter y operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. see the applications information section for details. a general purpose temperature diode is included inside the module to monitor the temperature of the module. see the applications information section for details. the switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. see the applications information section for details. lt m4650a 4650afb
13 for more information www.linear.com/ltm4650a the typical ltm4650 a application circuit is shown in figure? 32. external component selection is primarily determined by the maximum load current and output voltage. refer to table 6 for specific external capacitor requirements for particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4650a is capable of 98% duty cycle, but the v in to v out minimum dropout is still shown as a function of its load current and will limit output cur - rent capability related to high duty cycle on the top side switch. minimum on-time t on(min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency. t on(min) is specified in the electrical parameters as 90ns. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k? internal feedback resistor connects between the v outs1 to v fb1 and v outs2 to v fb2 . it is very important that these pins be connected to their respective outputs for proper feedback regulation. overvoltage can occur if these v outs1 and v outs2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. the output voltage will default to 0.6v with no feedback resistor on either v fb1 or v fb2 . adding a resistor r fb from v fb pin to gnd programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out 0.6v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5v r fb open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k for parallel operation of multiple channels the same feed - back setting resistor can be used for the parallel design. this is done by connecting the v outs1 to the output as shown in figure 2, thus tying one of the internal 60.4k applications information resistors to the output. all of the v fb pins tie together with one programming resistor as shown in figure 2. in parallel operation, the v fb pins have an i fb current of 20na maximum each channel. to reduce output voltage error due to this current, an additional v outs pin can be tied to v out , and an additional r fb resistor can be used to lower the total thevenin equivalent resistance seen by this current. for example in figure 2, the total thevenin equivalent resistance of the v fb pin is ( 60.4k//r fb ), which is 30.2k where r fb is equal to 60.4k for a 1.2v output. four phases connected in parallel equates to a worse case feedback current of 4 ? i fb = 80na maximum. the voltage error is 80na ? 30.2k = 2.4mv . if v outs2 is connected, as shown in figure 2, to v out , and another 60.4k resistor is connected from v fb2 to ground, then the voltage error is reduced to 1.2mv. if the voltage error is acceptable then no additional connections are necessary. the onboard 60.4k resistor is 0.5% accurate and the v fb resistor can be chosen by the user to be as accurate as needed. all comp pins are tied together for current sharing between the phases. the track/ss pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. the soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. see output voltage tracking section. figure 2. 4-phase parallel configurations 4650a f02 60.4k track1 track2 v out1 v outs1 v fb1 v fb2 comp1 4 paralleled outputs for 1.2v at 100a optional connection comp2 v outs2 v out2 60.4k 60.4k track1 track2 0.1f v out1 v outs1 v fb1 v fb2 comp1 comp2 v outs2 v out2 60.4k ltm4650a ltm4650a r fb 60.4k optional r fb 60.4k use to lower total equivalent resistance to lower i fb voltage error lt m4650a 4650afb
14 for more information www.linear.com/ltm4650a applications information input capacitors the ltm4650 a module should be connected to a low ac- impedance dc source. for the regulator input, two 22f input ceramic capacitors per channel are used for rms ripple current. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long in - ductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1 ? d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated electrolytic aluminum capacitor, polymer capacitor. output capacitors the ltm4650a is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output volt - age ripple and transient requirements. c out can be a low esr tantalum capacitor, the low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 300f to 800f per output channel. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 6 shows a matrix of different output voltages and output capacitors to mini - mize the voltage droop and overshoot during a 25% load step. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient per formance. stability criteria are considered in the table 6 matrix, and the analog devices ltpowercad design tool will be provided for stability analysis. multiphase operation will reduce effective output ripple as a function of the num - ber of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. the analog devices module power design t ool can calculate the output ripple reduction as the number of implemented phases increases by n times. a small value 10? to 50? resistor can be place in series from v out to the v outs pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. the same resistor could be place in series from v out to diffp and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. burst mode operation the ltm4650 a is capable of burst mode operation on each regulator in which the power mosfets operate in - termittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. burst mode operation is enabled with the mode_pllin pin floating. during this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera - tion even though the voltage at the comp pin indicates a lower value. the voltage at the comp pin drops when the inductor s average current is greater than the load requirement. as the comp voltage drops below 0.5v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off. the load current is now being supplied from the output capacitors. when the output voltage drops, causing comp to rise above 0.5v , the internal sleep line goes low, and the ltm4650 a resumes normal operation. the next os - cillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high effi - ciency at intermediate currents are desired, pulse-skipping lt m4650a 4650afb
15 for more information www.linear.com/ltm4650a applications information mode should be used. pulse-skipping operation allows the ltm4650 a to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. this mode will maintain higher effective frequencies thus lower output ripple and lower noise than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to gnd. in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4650as output voltage is in regulation. either regulator can be configured for force continuous mode. multiphase operation for output loads that demand more than 25a of current, two outputs in ltm4650 a or even multiple ltm4650 as can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. the mode_pllin pin allows the ltm4650 a to synchronize to an external clock (between 250khz and 780khz) and the internal phase-locked-loop allows the ltm4650a to lock onto incoming clock phase as well. the clkout signal can be connected to the mode_pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phasmd pin to intv cc , sgnd, or (floating) generates a phase difference (between mode_pllin and clkout) of 120 degrees, 60 degrees, or 90 degrees respectively . a total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin of each ltm4650a chan - nel to different levels. figure 3 shows a 2-phase design, 4- phase design and a 6-phase design example for clock phasing with the phasmd table. figure 3. examples of 2-phase, 4-phase, and 6-phase operation with phasmd table 4650a f03 v out2 180 phase 0 phase mode_pllin v out1 phasmd clkout 2-phase design 4-phase design 6-phase design 90 degree float v out2 180 phase 0 phase float mode_pllin v out1 phasmd clkout v out2 270 phase 90 phase float mode_pllin v out1 phasmd clkout 60 degree 60 degree v out2 180 phase 0 phase sgnd mode_pllin v out1 phasmd clkout v out2 240 phase 60 phase sgnd mode_pllin v out1 phasmd clkout v out2 300 phase 120 phase float mode_pllin v out1 phasmd clkout phasmd sgnd controller1 controller2 clkout float intv cc 0 0 0 180 180 240 60 90 120 lt m4650a 4650afb
16 for more information www.linear.com/ltm4650a applications information a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by , the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. the ltm4650 a device is an inherently current mode con - trolled device, so parallel modules will have very good cur - rent sharing. this will balance the thermals on the design. connect the comp pins, fb pins, track/ss pin and v out pins from different modules together. see figure 33 and 35 for examples of parallel operation. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure?4 shows this graph. figure 4. input rms current ratios to dc load current as a function of duty cycle duty factor (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4650a f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase lt m4650a 4650afb
17 for more information www.linear.com/ltm4650a applications information frequency selection and phase-lock loop (mode_pllin and f set pins) the ltm4650 a device is operated over a range of frequen - cies to improve power conversion efficiency. it is recom - mended to operate the module at 300khz to 750khz over different input and output range for the best efficiency and inductor current ripple. the ltm4650 a switching frequency can be set with an external resistor from the f set pin to sgnd. an accurate 10a current source into the resistor will set a voltage that programs the frequency or a dc voltage can be applied. figure 5 shows a graph of frequency setting verses programming voltage. an external clock can be applied to the mode_pllin pin from 0v to intv cc over a frequency range of 250khz to 780khz. the clock input high threshold is 1.6v and the clock input low threshold is 1v . the ltm4650a has the pll loop filter components on board. the frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. both regulators will operate in continuous mode while being externally clock. the output of the pll phase detector has a pair of comple - mentary current sources that charge and discharge the internal filter network. when the external clock is applied then the f set frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. when no external clock is applied, then the internal switch is on, thus connecting the external f set frequency set resistor for free run operation. minimum on-time minimum on-time t on is the smallest time duration that the ltm4650 a is capable of turning on the top mosfet on either channel. it is determined by internal timing delays, and the gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple and current will increase. the on-time can be increased by lowering the switching frequency. a good rule of thumb is to keep on-time longer than 110ns. soft-start and output voltage tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a ca - pacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 1.3a current source will charge up the external soft-start capacitor towards intv cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 1.3a where c ss is the capacitance on the track/ss pin. cur - rent foldback and forced continuous mode are disabled during the soft-start process. figure 5. operating frequency vs f set pin voltage f set pin voltage (v) 0 frequency (khz) 900 800 600 400 100 200 700 500 300 0 2 4650a f05 2.5 1 1.5 0.5 lt m4650a 4650afb
18 for more information www.linear.com/ltm4650a applications information output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 6 shows an example waveform where the slave regulator s output slew rate is proportional to the masters. since the slave regulators track/ss is connected to the master s output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6v, the slave output voltage and the master output voltage should satisfy the following equation during start-up: v out(sl) ? r fb(sl) r fb(sl) + 60.4k = v out(ma) ? r tr(bot) r tr(top) +r tr(bot) the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure 7. following the previous equation, the ratio of the masters output slew rate (mr) to the slaves output slew rate (sr) is determined by: mr sr = r fb(sl) r fb(sl) + 60.4k r tr(bot) r tr(top) +r tr(bot) for example, v out(ma) = 1.5v, mr = 1.5v/ 1ms and v out(sl) = 3.3v , sr = 3.3v/1ms. from the equation, we could solve that r tr(top) = 60.4k and r tr(bot) = 40.2k are a good combination for the ratiometric tracking. the track/ss pin will have the 2a current source on when a resistive divider is used to implement tracking on the slave regulator. this will impose an offset on the track/ss pin input. smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track/ss pin offset to a negligible value. coincident output tracking can be recognized as a special ratiometric output tracking in which the masters output slew rate (mr) is the same as the slaves output slew rate (sr), waveform as shown in figure 8. from the equation, we could easily find that, in coincident tracking, the slave regulator s track/ss pin resistor divider is always the same as its feedback divider: r fb(sl) r fb(sl) + 60.4k = r tr(bot) r tr(top) +r tr(bot) for example, r tr(top) = 60.4k and r tr(bot) = 13.3k is a good combination for coincident tracking for a v out(ma) = 1.5v and v out(sl) = 3.3v application. figure 6. output ratiometric tracking waveform time slave output master output output voltage 4650a f06 lt m4650a 4650afb
19 for more information www.linear.com/ltm4650a applications information figure 8. output coincident tracking waveform figure 7. example of output tracking application circuit time master output slave output output voltage 4650a f08 4650a f07 ltm4650a v in temp track1 track2 run1 run2 f set c8 470f 6.3v r fb(sl) 13.3k r2 10k c6 100f 6.3v 3 phasmd v out1 v outs1 v fb1 v fb2 comp1 comp2 v outs2 v out2 pgood2 mode_pllin intv cc pgood1 pgood1 intv cc sgnd gnd v out1 (master) 1.5v ramp time t softstart = (c ss /1.3a) ? 0.6 diffp diffn diffout 40.2k pgood2 slave v out1 (master) 1.5v 25a c7 470f 6.3v c5 100f 6.3v 3 r4 140k r tr(top) 60.4k 4.5v to 16v intermediate bus r6 100k c ss c1 22f 25v r tr(bot) 40.2k c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f r9 10k intv cc v out2 (slave) 3.3v 25a pins not used in this circuit: clkout extv cc , sw1, sw2 lt m4650a 4650afb
20 for more information www.linear.com/ltm4650a applications information power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. stability compensation the module has already been internally compensated for all output voltages. table 6 is provided for most applica - tion requirements. ltpowercad will be provided for other control loop optimization. run enable the run pins have an enable threshold of 1.4v maximum, typically 1.25v with 150mv of hysteresis. they control the turn on each of the channels and intv cc . these pins can be pulled up to v in for 5v operation, or a 5v zener diode can be placed on the pins and a 10k to 100k resis - tor can be placed up to higher than 5v input for enabling the channels. there is 1a pull-up current for each run pin. the ltm4650a will turn on with run floating. please note run has a 6v abs max voltage rating. the run pins can also be used for output voltage sequencing. in parallel operation the run pins can be tie together and controlled from a single control. see the t ypical applica - tion circuits in figure 32. int v cc and extv cc the ltm4650 a module has an internal 5v low dropout regulator that is derived from the input voltage. this regu - lator is used to power the control circuitry and the power mosfet drivers. this regulator can sour ce up to 70ma, and typically uses ~30ma for powering the device at the maximum frequency. this internal 5v supply is enabled by either run1 or run2. extv cc allows an external 5v supply to power the ltm4650a and reduce power dissipation from the internal low dropout 5v regulator. the power loss savings can be calculated by: (v in C 5v) ? 30ma = ploss extv cc has a threshold of 4.7v for activation, and a maximum rating of 6v . when using a 5v input, connect this 5v input to extv cc also to maintain a 5v gate drive level. extv cc must sequence on after v in , and extv cc must sequence off before v in . differential remote sense amplifier an accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. this is especially true for high current loads. the amplifier can be used on one of the two channels, or on a single parallel output. it is very important that the diffp and diffn are connected properly at the output, and diffout is connected to either v outs1 or v outs2 . in parallel operation, the diffp and diffn are connected properly at the output, and diffout is connected to one of the v outs pins. review the parallel schematics in figure 33 and review figure 2. please note diffamp can be used for 3.3v outputs. sw pins the sw pins are generally for testing purposes by moni - toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combina - tion is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated : z (l) = 2fl, lt m4650a 4650afb
21 for more information www.linear.com/ltm4650a temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 4650a f09 125 i d = 100a figure 9. diode voltage v d vs temperature t(k) for different bias currents applications information where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z (c) = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. temperature monitoring a diode connected pnp transistor is used for the temp monitor function by monitoring its voltage over tempera - ture. the temperature dependence of this diode voltage can be understood in the equation : v d = nv t ln i d i s ? ? ? ? ? ? where v t is the thermal voltage (k t /q), and n, the ideality factor, is 1 for the diode connected pnp transistor being used in the ltm4650a. i s is expressed by the typical empirical equation: i s = i 0 exp C v g0 v t ? ? ? ? ? ? ? ? ? ? where i 0 is a process and geometry dependent current, (i 0 is typically around 20k orders of magnitude larger than i s at room temperature) and v g0 is the band gap voltage of 1.2v extrapolated to absolute zero or C273c. if we take the i s equation and substitute into the v d equa- tion, then we get: v d = v g0 C kt q ? ? ? ? ? ? ln i 0 i d ? ? ? ? ? ? , v t = kt q the expression shows that the diode voltage decreases (linearly if i 0 were constant) with increasing temperature and constant diode current. figure 9 shows a plot of v d vs temperature over the operating temperature range of the ltm4650a. if we take this equation and differentiate it with respect to temperature t, then: dv d dt = C v g0 C v d t this dv d /d t term is the temperature coefficient equal to about C2mv /k or C2mv/c. the equation is simplified for the first order derivation. solving for t, t = C(v g0 C v d )/(dv d /d t ) provides the temperature. 1st example : figure 9 for 27 c , or 300k the diode voltage is 0.598v, thus, 300k = C(1200mv C 598mv)/ C2.0 mv/k) 2nd example: figure 9 for 75c , or 350k the diode voltage is 0.50v, thus, 350k = C(1200mv C 500mv)/ C2.0mv/k) converting the kelvin scale to celsius is simply taking the kelvin temp and subtracting 273 from it. a typical for ward voltage is given in the electrical charac - teristics section of the data sheet, and figure 9 is the plot of this for ward voltage. measure this forward voltage at 27c to establish a reference point. then using the above expression while measuring the forward voltage over temperature will provide a general temperature monitor. connect a resistor between temp and v in to set the cur - rent to 100a. see figure 33 for an example. lt m4650a 4650afb
22 for more information www.linear.com/ltm4650a applications information thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd51-9 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per formed on a module package mounted to a hardware test board also defined by jesd51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd 51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal per formance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef - ficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don t generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal re - sistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. a graphical representation of the aforementioned thermal resistances is given in figure 10; blue resistances are contained within the module regulator, whereas green resistances are external to the module. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclu - sively through the top or exclusively through bottom of the module as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. lt m4650a 4650afb
23 for more information www.linear.com/ltm4650a applications information figure 10. graphical representation of jesd51-12 thermal coefficients within a sip (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software-defined jedec environment consistent with jesd51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the module with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to cor - relate quite well with the module model with no airflow or heat sinking in a properly define chamber . this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. the ltm4650 a module has been designed to effectively remove heat from both the top and bottom of the pack - age. the bottom substrate material has very low thermal resistance to the printed cir cuit board. an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. figure 11 shows the thermal image of the ltm4650a, without airflow, without heat sink, running paralleled from 12v to 1v at 50a with around 87.3% efficiency and 7.2w power loss. figure 12 shows the thermal image of the ltm4650 a, with 200lfm airflow and external heat sink, running paralleled form 12v to 5v at 50a with around 95% efficiency and 13w power loss. 4650a f10 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance lt m4650a 4650afb
24 for more information www.linear.com/ltm4650a applications information figure 11. thermal image 12v to 1v, 50a with no airflow without heat sink figure 12. thermal image 12v to 5v, 50a with 200lfm airflow without heat sink safety considerations the ltm4650 a modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support over current protection. a temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the run pin. power derating the 1v, 1.8v, 3.3v and 5v power loss curves in figures?14 to 17 can be used in coordination with the load current derating curves in figures 18 to 31 for calculating an ap - proximate ja thermal resistance for the ltm4650a with various heat sinking and airflow conditions. the power loss curves are taken at room temperature, and are increased with a 1.2 multiplicative factor at 125c. the derating curves are plotted with c h1 and ch2 in parallel single output operation starting at 50a of load with low ambient temperature. the output voltages are 1v to 5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at ~120c maximum while lowering output current or power while increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure 22, the load current is derated to ~25a at ~90c with no air or heat sink and the power loss for the 12v to 1.8v at 25a output is a ~4.4w loss. the 4.4w loss is calculated with the ~3.7w room temperature loss from the 12v to 1.8v power loss curve at 25a, and the 1.2 multiplying factor at 120c ambient. if the 90c ambient temperature is subtracted from the 120c junction temperature, then the difference of 30c divided 4.4w equals a 6.8c/w ja thermal resistance. table 2 specifies a 7c /w value which is pretty close. the airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. tables 2 to 5 provide equivalent thermal resistances for 1v to 5v outputs with and without airflow and heat sinking. lt m4650a 4650afb
25 for more information www.linear.com/ltm4650a applications information the derived thermal resistances in tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. the printed circuit board is a 1.6mm thick four layer board with two ounce copper for all four layers. the pcb dimensions are 101mm 114mm . the bga heat sinks are listed in table 3. layout checklist/example the high integration of ltm4650a makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessar y. ? use large pcb copper areas for high current paths, including v in , gnd, v out1 and v out2 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? t o minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure 13 gives a good example of the recommended layout. figure 13. recommended pcb layout a 1 2 v out1 v out2 gnd sgnd cntrl 4650a f13 gnd gnd v in 3 4 5 6 7 8 9 10 11 12 b c d e k l m f g h j c out1 c out2 c in1 c in2 lt m4650a 4650afb
26 for more information www.linear.com/ltm4650a applications information table 2. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 18, 19 5, 12 figure 14 0 none 7 figures 18, 19 5, 12 figure 14 200 none 6 figures 18, 19 5, 12 figure 14 400 none 5.5 figures 20, 21 5, 12 figure 14 0 bga heat sink 6.5 figures 20, 21 5, 12 figure 14 200 bga heat sink 5 figures 20, 21 5, 12 figure 14 400 bga heat sink 4 table 4. 3.3v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 26, 27 5, 12 figure 16 0 none 7 figures 26, 27 5, 12 figure 16 200 none 6 figures 26, 27 5, 12 figure 16 400 none 5.5 figures 28, 29 5, 12 figure 16 0 bga heat sink 6.5 figures 28, 29 5, 12 figure 16 200 bga heat sink 5 figures 28, 29 5, 12 figure 16 400 bga heat sink 4 table 3. 1.8v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 22, 23 5, 12 figure 15 0 none 7 figures 22, 23 5, 12 figure 15 200 none 6 figures 22, 23 5, 12 figure 15 400 none 5.5 figures 24, 25 5, 12 figure 15 0 bga heat sink 6.5 figures 24, 25 5, 12 figure 15 200 bga heat sink 4 figures 24, 25 5, 12 figure 15 400 bga heat sink 3.5 table 5. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 30 12 figure 17 0 none 7 figures 30 12 figure 17 200 none 6 figures 30 12 figure 17 400 none 5.5 figures 31 12 figure 17 0 bga heat sink 6.5 figures 31 12 figure 17 200 bga heat sink 4 figures 31 12 figure 17 400 bga heat sink 3.5 heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com lt m4650a 4650afb
27 for more information www.linear.com/ltm4650a applications information table 6. output voltage response vs component matrix (refer to figure 33) load step typical measured values 2-phase single output solution c in (ceramic) c out (ceramic) c out (bulk) vendors value part number vendors value part number vendors value part number murata 22f, 16v, x5r, 1210 grm32er61c226ke20l murata 100f, 6.3v, x5r, 1210 grm32er60j107me20l panasonic 470f, 6.3v 10m 6tpf470mah 1 murata 22f, 16v, x5r, 1206 grm31cr61c226ke15k murata 220f, 4v, x5r, 1206 grm31cr60g227m panasonic 470f, 2.5v 3m eefgx0e4tir 2 tdk 22f, 16v, x5r, 1210 c3225x5r1c226m250aa taiyo yuden 100f, 6.3v, x5r, 1210 jmk325bj107mm-t taiyo yuden 220f, 4v, x5r, 1210 amk325abj227mm-t 25% load step (0a to 12.5a), ceramic output cap only solutions v in v out c in 3 (bulk) c in (ceramic) c out (bulk) c out (ceramic) feed-forward capacitor (c ff ) peak-peak deviation (v pk-pk ) settling time (t settle ) load step load step slew rate r fb (k) freq (khz) 12v 1v 150f 22f 4 none 100f16 47pf 102mv 50s 12.5a 10a/s 90.9 300khz 12v 1.2v 150f 22f 4 none 100f16 47pf 92mv 50s 12.5a 10a/s 60.4 400khz 12v 1.5v 150f 22f 4 none 100f16 47pf 105mv 50s 12.5a 10a/s 40.2 400khz 12v 1.8v 150f 22f 4 none 100f16 47pf 109mv 50s 12.5a 10a/s 30.2 500khz 12v 2.5v 150f 22f 4 none 100f16 47pf 134mv 60s 12.5a 10a/s 19.1 500khz 12v 3.3v 150f 22f 4 none 100f16 47pf 161mv 60s 12.5a 10a/s 13.3 600khz 12v 5v suggest to use poscap + ceramic cap 25% load step (0a to 12.5a), poscap+ceramic output cap solutions v in v out c in 3 (bulk) c in (ceramic) c out (bulk) c out (ceramic) feed-forward capacitor (c ff ) peak-peak deviation (v pk-pk ) settling time (t settle ) load step load step slew rate r fb (k) freq (khz) 12v 1v 150f 22f 4 470f4 2 100f8 none 82mv 50s 12.5a 10a/s 90.9 300khz 12v 1.2v 150f 22f 4 470f4 2 100f8 none 80mv 50s 12.5a 10a/s 60.4 400khz 12v 1.5v 150f 22f 4 470f4 2 100f8 none 92mv 60s 12.5a 10a/s 40.2 400khz 12v 1.8v 150f 22f 4 470f4 2 100f8 none 97mv 70s 12.5a 10a/s 30.2 500khz 12v 2.5v 150f 22f 4 470f4 2 100f8 none 117mv 70s 12.5a 10a/s 19.1 500khz 12v 3.3v 150f 22f 4 470f4 1 100f8 none 127mv 80s 12.5a 10a/s 13.3 600khz 12v 5v 150f 22f 4 470f4 1 100f8 none 167mv 100s 12.5a 10a/s 8.25 700khz notes 1 and 2. different (bulk) c out are used. see part number in table 6. note 3. c in (bulk) may be required with long pcb traces. lt m4650a 4650afb
28 for more information www.linear.com/ltm4650a applications information figure 14. 1.0v out power loss curve figure 15. 1.8v out power loss curve figure 16. 3.3v out power loss curve figure 17. 5v out power loss curve figure 18. 12v to 1v derating curve, no heat sink figure 19. 5v to 1v derating curve, no heat sink figure 20. 12v to 1v derating curve, bga heat sink figure 21. 5v to 1v derating curve, bga heat sink figure 22. 12v to 1.8v derating curve, no heat sink v in = 12v v in = 5v v in = 12v v in = 5v v in = 12v v in = 5v v in = 12v 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm lt m4650a 4650afb 35 9 10 11 12 13 14 15 power loss (w) 4650a f17 ambient temperature (c) 40 30 40 50 60 70 80 90 100 110 120 45 0 10 20 30 40 50 60 load current (a) 4650a f18 ambient temperature (c) 50 30 40 50 60 70 80 90 100 110 120 0 0 10 20 30 40 50 60 load current (a) 4650a f19 ambient temperature (c) 1 30 40 50 60 70 80 90 100 110 120 2 0 10 20 30 40 50 60 load current (a) 4650a f20 ambient temperature (c) 3 30 40 50 60 70 80 90 100 110 120 4 0 10 20 30 40 50 60 load current (a) 4650a f21 ambient temperature (c) 5 30 40 50 60 70 80 90 100 110 120 load current (a) 6 0 10 20 30 40 50 60 load current (a) 4650a f22 7 8 9 10 power loss (w) 4650a f14 load current (a) 0 5 0 10 15 20 25 30 35 40 45 50 0 5 1 2 3 4 5 6 7 8 9 10 10 power loss (w) 4650a f15 load current (a) 0 5 10 15 20 25 30 15 35 40 45 50 0 1 2 3 4 5 20 6 7 8 9 10 11 12 power loss (w) 4650a f16 load current (a) 25 0 5 10 15 20 25 30 35 40 45 30 50 0 1 2 3 4 5 6 7 8
29 for more information www.linear.com/ltm4650a applications information figure 23. 5v to 1.8v derating curve, no heat sink figure 24. 12v to 1.8v derating curve, bga heat sink figure 25. 5v to 1.8v derating curve, bga heat sink figure 26. 12v to 3.3v derating curve, no heat sink figure 27. 5v to 3.3v derating curve, no heat sink figure 28. 12v to 3.3v derating curve, bga heat sink figure 29. 5v to 3.3v derating curve, bga heat sink figure 30. 12v to 5v derating curve, no heat sink figure 31. 12v to 5v derating curve, bga heat sink 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm 400lfm 200lfm 0lfm lt m4650a 4650afb 100 4650a f27 ambient temperature (c) 30 40 50 60 70 80 90 100 110 110 120 0 10 20 30 40 50 60 load current (a) 120 4650a f28 ambient temperature (c) 30 40 50 60 70 80 90 100 0 110 120 0 10 20 30 40 50 60 load current (a) 10 4650a f29 ambient temperature (c) 30 40 50 60 70 80 90 100 20 110 120 0 10 20 30 40 50 60 load current (a) 30 4650a f30 ambient temperature (c) 30 40 50 60 70 80 90 100 40 110 120 0 10 20 30 40 50 60 load current (a) 50 4650a f31 60 ambient temperature (c) load current (a) 4650a f23 ambient temperature (c) 30 40 50 60 70 80 90 30 100 110 120 0 10 20 30 40 50 60 40 load current (a) 4650a f24 ambient temperature (c) 30 40 50 60 70 80 90 50 100 110 120 0 10 20 30 40 50 60 60 load current (a) 4650a f25 ambient temperature (c) 30 40 50 60 70 80 90 70 100 110 0 10 20 30 40 50 60 load current (a) 80 4650a f26 ambient temperature (c) 30 40 50 60 70 80 90 100 90 110 120 0 10 20 30 40 50 60 load current (a)
30 for more information www.linear.com/ltm4650a figure 32. typical 4.5v in to 16v in , 1.5v and 1.2v at 25a outputs typical applications 4650a f32 ltm4650a v in temp track1 track2 run1 run2 f set r fb2 60.4k r2 10k c out1 100f 6.3v 8 phasmd v out1 v outs1 v fb1 v fb2 v outs2 v out2 pgood2 mode_pllin intv cc pgood1 pgood1 intv cc sgnd gnd track1 track2 diffp diffn diffout r fb1 40.2k pgood2 v out2 1.2v at 25a c ff1 * 47pf c ff2 * 47pf c out1 100f 6.3v 8 r4 90.9k 4.5v to 16v intermediate bus r7 100k c5 0.1f c9 0.1f c in 22f 25v 4 c10 4.7f v out1 1.5v at 25a r3 10k intv cc + c in (opt) v in 4.5v to 16v *see table 4 pins not used in this circuit: clkout, extv cc , sw1, sw2 comp1 comp2 lt m4650a 4650afb
31 for more information www.linear.com/ltm4650a figure 33. ltm4650a 2-phase, 1v at 50a design 4650a f33 ltm4650a v in temp run1 run2 track1 track track2 f set r5 90.9k c out1 100f 6.3v 16 phasmd v out1 v outs1 v fb1 v fb2 v out2 pgood2 pgood mode_pllin intv cc pgood1 pgood 47pf r2 10k intv cc sgnd gnd diffn diffp diffout r4 75k c9 0.1f c in 22f 25v 4 c10 4.7f intv cc a/d c v in r t v in 4.5v to 16v v out 1v 50a r t = v in 100a run load 1v at 50a pins not used in this circuit: clkout, extv cc , sw1, sw2, v outs2 comp1 comp2 typical applications lt m4650a 4650afb
32 for more information www.linear.com/ltm4650a typical applications figure 34. ltm4650a 2.5v and 3.3v output with tracking function 4650a f34 ltm4650a v in temp track1 track2 f set r2 10k phasmd v out1 v outs1 v fb1 v outs2 v out2 v fb2 mode_pllin intv cc pgood1 pgood1 intv cc sgnd gnd pgood2 v out1 2.5v diffn diffp diffout r5 19.1k v out2 3.3v at 25a c out1 220f 4v 2 r4 140k r9 60.4k r6 100k c5 0.1f c1 22f 25v r7 13.3k c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f v out1 2.5v 25a v in 4.5v to 16v c out1 220f 4v 2 intv cc pgood2 10k 13.3k load 3.3v at 25a load 2.5v at 25a 470f 4v + 470f 4v + pins not used in this circuit: clkout, extv cc , sw1, sw2, run1 run2 comp1 comp2 lt m4650a 4650afb
33 for more information www.linear.com/ltm4650a typical applications figure 35. ltm4650a 4-phase, 1.2v at 100a 4650a f35 ltm4650a u1 v in temp run1 run run2 track1 track run track2 f set r5 60.4k r2 5k c out1 100f 4v 16 v out1 v outs1 v fb1 v fb2 comp1 comp2 comp v out2 pgood2 pgood mode_pllin clkout clk1 clk1 intv cc pgood1 pgood sgnd gnd diffp diffn diffout r4 75k r6 100k c2 22f 25v 3 c10 4.7f ltm4650a u2 v in temp run1 run2 track1 track2 f set c out1 100f 4v 16 v in 4.5v to 16v v out1 v outs1 v fb1 v fb2 comp1 v fb comp comp2 phasmd phasmd v out2 v outs2 v outs2 pgood2 pgood mode_pllin intv cc clkout pgood1 pgood sgnd gnd diffp diffn r10 75k r9 100k c19 0.22f c15 22f 25v 3 c16 4.7f intv cc track v fb 47pf intv cc v out 1.2v 100a pins not used in circuit ltm4650a u1: extv cc , sw1, sw2 pins not used in circuit ltm4650a u2: diffout, extv cc , sw1, sw2 lt m4650a 4650afb
34 for more information www.linear.com/ltm4650a ltm4650a component lga and bga pinout package description pin id function pin id function pin id function pin id function pin id function pin id function a1 v out1 b1 v out1 c1 v out1 d1 gnd e1 gnd f1 gnd a2 v out1 b2 v out1 c2 v out1 d2 gnd e2 gnd f2 gnd a3 v out1 b3 v out1 c3 v out1 d3 gnd e3 gnd f3 gnd a4 v out1 b4 v out1 c4 v out1 d4 gnd e4 gnd f4 mode_pllin a5 v out1 b5 v out1 c5 v out1s d5 vfb1 e5 track1 f5 run1 a6 gnd b6 gnd c6 f set d6 sgnd e6 comp1 f6 sgnd a7 gnd b7 gnd c7 sgnd d7 vfb2 e7 comp2 f7 sgnd a8 v out2 b8 v out2 c8 v out2s d8 track2 e8 diffp f8 diffout a9 v out2 b9 v out2 c9 v out2 d9 gnd e9 diffn f9 run2 a10 v out2 b10 v out2 c10 v out2 d10 gnd e10 gnd f10 gnd a11 v out2 b11 v out2 c11 v out2 d11 gnd e11 gnd f11 gnd a12 v out2 b12 v out2 c12 v out2 d12 gnd e12 gnd f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 gnd k1 gnd l1 gnd m1 gnd g2 sw1 h2 gnd j2 v in k2 v in l2 v in m2 v in g3 gnd h3 gnd j3 v in k3 v in l3 v in m3 v in g4 phasemd h4 gnd j4 v in k4 v in l4 v in m4 v in g5 clkout h5 gnd j5 gnd k5 gnd l5 v in m5 v in g6 sgnd h6 gnd j6 temp k6 gnd l6 vin m6 v in g7 sgnd h7 gnd j7 extv cc k7 gnd l7 v in m7 v in g8 pgood2 h8 intv cc j8 gnd k8 gnd l8 v in m8 v in g9 pgood1 h9 gnd j9 v in k9 v in l9 v in m9 v in g10 gnd h10 gnd j10 v in k10 v in l10 v in m10 v in g11 sw2 h11 gnd j11 v in k11 v in l11 v in m11 v in g12 gnd h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd lt m4650a 4650afb
35 for more information www.linear.com/ltm4650a package description please refer to http://www.linear.com/product/ltm4650a#packaging for the most recent package drawings. lt m4650a 4650afb
36 for more information www.linear.com/ltm4650a bga package 144-lead (16mm 16mm 5.01mm) (reference ltc dwg # 05-08-1523 rev a) package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes d e b e e b f g bga 144 0517 rev a tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a pin 1 l k j h g f e d c b m a 1 2 3 4 5 6 7 8 10 9 11 12 suggested pcb layout top view 0.0000 0.0000 0.630 0.025 ? 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail a ?b (144 places) a detail b package side view m x yzddd m zeee a2 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature 6 see notes symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 total number of balls: 144 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! package description please refer to http://www.linear.com/product/ltm4650a#packaging for the most recent package drawings. lt m4650a 4650afb
37 for more information www.linear.com/ltm4650a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 07/17 added pin compatible feature 1 b 10/17 added lga package 1, 2, 35, 38 lt m4650a 4650afb
38 for more information www.linear.com/ltm4650a lt 1017 rev b ? printed in usa www.linear.com/ltm4650a ? analog devices, inc. 2017 related parts package photo design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation t ools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. sear ch using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management analog devicess family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. part number description comments ltm4630a lower current than ltm4650a; up to 5.3v out , dual 18a or single 36a pin compatible with ltm4650a; 4.5v v in 15v, 0.6v v out 5.3v, 16mm 16mm 4.41mm (lga) lt m4630-1 lower current and lower v out(max) than ltm4650a with external compensation. dual 18a or single 36a. 0.8% (C1a) or 1.5% (C1b) v out accuracy 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 5.01mm (bga) ltm4630 lower current, lower v out(max) than ltm4650a; dual 18a or single 36a pin compatible with ltm4650a; 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 4.41mm (lga), 16mm 16mm 5.01mm (bga) ltm4620a lower current than ltm4650a; up to 5.3v out , dual 13a or single 26a. pin compatible with ltm4650a. 4.5v v in 16v, 0.6v v out 5.3v, 15mm 15mm 4.41mm (lga), 15mm 15mm 5.01mm (bga) ltm4636 single 40a module regulator 4.7v v in 15v. 0.6v v out 3.3v. 16mm 16mm 7.07mm (bga) ltm4677 dual 18a or single 36a with psm 4.5v v in 16v, 0.5v v out 1.8v. 16mm 16mm 5.01mm (bga) LTM4644 quad 4a 4v v in 14v, 0.6v v out 5.5v. 9mm 15mm 5.01mm (bga) ltm4639 lower v in (2.375v v in 7v), 20a 0.6v v out 5.5v. 15mm 15mm 4.92mm (bga) lga bga lt m4650a 4650afb

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